==============================================================
Guild: wafer.space Community
Channel: ℹ️ - Information / general / Not yet, it's mainly blinky and the test
After: 2026-03-31 11:59 p.m.
Before: 2026-05-01 12:00 a.m.
==============================================================

[2026-04-06 2:34 p.m.] mole99



[2026-04-06 2:34 p.m.] mole99
Well, before you go for a tapeout, it is probably a good idea to validate that the fabric can support more complex designs.

From what I can see, your switch matrix only has direct connections to neighboring tiles. You may need connections that span multiple tiles to improve connectivity, otherwise you may end up with unroutable situations.

After all, 90% of an FPGA is just the routing 😉


[2026-04-06 2:37 p.m.] thecomputerguy
Yeah, I've been able to verify most of the design. I've asked a couple people to review and give feedback but I haven't heard back from them yet.


[2026-04-06 2:38 p.m.] thecomputerguy
I'm mainly focused on making the tapeout workflow not be as heavy and slow.


[2026-04-06 2:41 p.m.] mole99
I see! I really dig the automated and reproducible build of the chip. I use LibreLane to build the FABulous FPGA reproducibly as well, but I only use Nix for the tools.


[2026-04-06 2:42 p.m.] mithro_
BTW Have you seen my ramberlings in https://docs.google.com/document/d/1n2YaYvHRq6sSTN80jMbDDu8qRKy45c0DJyZbVrDrv_o/edit?tab=t.0 ?

{Embed}
https://docs.google.com/document/d/1n2YaYvHRq6sSTN80jMbDDu8qRKy45c0DJyZbVrDrv_o/edit?tab=t.0
wafer.space - GF180MCU Fabulous FPGA
GF180MCU FABulous FPGA Goal Have a strong 5V tolerant FPGA / CPLD usable for legacy emulation projects.  Specifications   SRAM? Info about what SRAM amount is possible can be found @  Memory is something I am thinking about right now: Different PDKs have different memory options (size, features...
2026-04_media/AHkbwyLt1-sdZKGLTh5ge2xhMg3cz9DkeQ19EDFwGP-DD8DE


[2026-04-06 2:42 p.m.] thecomputerguy
Yeah so I looked at LibreLane and I see why it was made. However, I can get better utilization by splitting the tapeout workflow.


[2026-04-06 2:43 p.m.] thecomputerguy
This is what I've been working on. Each tile gets taped out and everything is placed together at the end.

{Attachments}
2026-04_media/HFMdaQMbgAA8apR-55771.png


[2026-04-06 2:43 p.m.] thecomputerguy
Interesting


[2026-04-06 2:44 p.m.] mithro_
See also my kinda silly spreadsheet at https://docs.google.com/spreadsheets/d/1KIqtzRaZbrWsbKwZqevY2elmVIz1gm5UJqOP75bxcOg/edit?gid=1500563840#gid=1500563840

{Embed}
https://docs.google.com/spreadsheets/d/1KIqtzRaZbrWsbKwZqevY2elmVIz1gm5UJqOP75bxcOg/edit?gid=1500563840
wafer.space - GF180MCU LUT sizing and configuration
2026-04_media/AHkbwyK_mLpBOgdCcFa2EYOgt3BZ1Fgg2hTe7APOmZ-9DF38


[2026-04-06 2:44 p.m.] mole99
Very nice! My LibreLane plugin also first implements the tile macros in parallel and then stitches the fabric: https://github.com/mole99/librelane_plugin_fabulous


[2026-04-06 2:45 p.m.] thecomputerguy
I get the benefit of being able to use a Nix cache and I can cache things much easily.


[2026-04-06 2:46 p.m.] thecomputerguy
Huh


[2026-04-06 2:47 p.m.] mithro_
@The Computer Guy - Don't worry if it doesn't make sense, I was just thinking about the problem by trying to pack standard cells together to get 100% density and not actually doing anything useful.


[2026-04-06 2:47 p.m.] thecomputerguy
Yeah, I was kinda gathering that


[2026-04-06 2:50 p.m.] mole99
Yeah, that is a nice approach! I use Make to build the tiles. In theory, I could also only rebuild what is needed, however, that hasn't been necessary so far since implementing all tiles doesn't take that long. But it's a good future improvement.

I also cache the tiles in the CI, see here for the HeiChips fabric: https://github.com/FPGA-Research/heichips25-tapeout/actions/runs/23842507549


==============================================================
Exported 16 message(s)
==============================================================